Supply voltage reduction in SRAMs: Impact on Static Noise Margins

Reducing leakage in memories is critical to reduce static power consumption in nanometric technologies. A wide-spread technique for reducing the leakage consists of lowering the supply voltage on the SRAM module. The paper investigates the effect of lowering the supply voltage on the robustness of a 6T SRAM cell, both in saturation and sub-threshold regimes. The static noise margin (SNM) is evaluated analytically and compared with HSPICE simulations for 130 nm, 90 nm and 65 nm Berkeley predictive technology models (BPTM) [9]. In addition, the impact of process variation is considered.