Title :
Measurement and analysis of variability in 45nm strained-Si CMOS technology
Author :
Liang-Teck Pang;Borivoje Nikolic
Author_Institution :
Electrical Engineering and Computer Sciences, University of California, Berkeley, USA
Abstract :
A test-chip in a low-power 45nm technology, featuring uniaxial strained Si, has been built to study variability in CMOS circuits. Systematic layout-induced variation, die-to-die (D2D), wafer-to-wafer (W2W) and within-die (WID) variability has been measured and analyzed. Delay is characterized using an array of ring-oscillators and transistor leakage current is measured with an on-chip ADC. Results show that systematic variations are small and layout-induced variation is dominated by strain effects.
Keywords :
"CMOS technology","Tensile strain","Tensile stress","MOS devices","Current measurement","Capacitive sensors","Lithography","Circuit testing","Leakage current","Dielectric substrates"
Conference_Titel :
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
Print_ISBN :
978-1-4244-2018-6
Electronic_ISBN :
2152-3630
DOI :
10.1109/CICC.2008.4672038
