Background ADC calibration in digital domain

A 100MS/s pipelined ADC is digitally calibrated by a slow ΣΔ ADC using a least-mean-square (LMS) algorithm. Both linear and nonlinear memoryless residue gain errors of the pipeline stages are adaptively corrected. With a 411kHz sinusoidal input, the peak SNDR improves from 28dB to 59dB and the SFDR improves from 29dB to 68dB. The complete 0.13μ ADC SoC occupies a die size of 3.7mm×4.7mm, and consumes a total power of 448mW.