A 15 MHz – 600 MHz, 20 mW, 0.38 mm2, fast coarse locking digital DLL in 0.13μm CMOS

A digital delay-locked-loop (DLL) suitable for generation of multiphase clocks in applications such as time-interleaved and pipelined ADCs locks in a very wide (40X) frequency range. The DLL provides 12 uniformly delayed phases that are free of false harmonic locking. The digital control loop has two stages: a fast-locking coarse acquisition is achieved in four cycles using binary search; a fine linear loop achieves low jitter (8.9 ps rms @ 600 MHz) and tracks PVT variations. The DLL consumes 20 mW and occupies a 470 μm X 800 μm area in 0.13μm CMOS.