DocumentCode :
3629663
Title :
A low-power programmable dynamic frequency divider
Author :
Jeremie Chabloz;David Ruffieux;Christian Enz
Author_Institution :
Swiss Center for Electronics and Microtechnology (CSEM), Neuch?tel, Switzerland
fYear :
2008
Firstpage :
370
Lastpage :
373
Abstract :
In this paper, a solution to realize a low-power programmable frequency divider using dynamic logic is proposed. By cascading compact dual-modulus divider slice with recursive feedback mechanisms, any dividing ratio is easily implemented. A 5-stages 0.18 mum CMOS implementation demonstrates a power consumption factor as low as 235 nW/MHz under 1.2 V supply for high dividing ratios.
Keywords :
"Frequency conversion","Phase locked loops","Clocks","Ring oscillators","Frequency synthesizers","CMOS logic circuits","Local oscillators","Switches","Injection-locked oscillators","Feedback"
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European
ISSN :
1930-8833
Print_ISBN :
978-1-4244-2361-3
Type :
conf
DOI :
10.1109/ESSCIRC.2008.4681869
Filename :
4681869
Link To Document :
بازگشت