PLD implementation of all-digital delay-locked loop

An all-digital delay-locked loop (DLL) suitable for implementation in programmable logic devices (PLD) is presented in this paper. All parts of DLL are created only from discrete digital elements. A digital controlled delay line (DCDL) is made from digital controlled delay elements (DCDE) by using LCELL (basic delay elements in ALTERA). A charge pump (CP) and a loop filter (LF) in the proposed circuit are replaced with a 3-bit up/down/hold counter. The proposed DLL is implemented and tested in ALTERA PLD EPM7128SLI10.