Test Structure Design, Extraction, and Impact Study of FEOL Capacitance Parameters in Advanced 45nm Technology

In the advanced Low Power (LP) CMOS technology nodes gate-to-soure/drain overlap capacitance (COV), gate-to-contact capacitance (CCO) and gate sidewall fringe capacitance (Cf) have become increasingly important component(s) of transistor parasitic. Accurate extraction and modeling of these parasitic are essential in accurate estimation of circuit performance. In this paper we describe test structure design and extraction of these parasitic components from silicon, which we later correlate to circuit performance. SPICE simulations were performed to substantiate the measurements as needed.