Propagation of I/O-variables in massively parallel processor arrays

The underlying design method for massively parallel processor arrays allows one to exploit parallelism in a broader range, because the I/O variables are not considered during the design process of a full-size array. As a consequence of this approach, a reallocation of the I/O ports of the I/O variables at the boundary processors of the processor array is necessary. Algorithms are described for the reallocation of the I/O ports at the array boundaries, leading to a minimal additional latency and taking systolic constraints into account. Integer linear programming is used to solve the optimization problems that arise.