Effects of /spl gamma/-irradiation and postirradiation thermal annealing in power VDMOSFETs

The behaviour of commercial n-channel power VDMOSFETs during /spl gamma/-ray irradiation and subsequent annealing at elevated temperature is investigated. The creation of positive oxide-trap charge dominates during irradiation, leading to negative threshold voltage shift. So called ´latent´ interface-trap buildup, observed during annealing after initial apparent saturation of interface-trap density, is identified as the main contributor to the threshold voltage rebound. At very late annealing times, a significant decrease in the number of interface traps occurs. Possible mechanisms for observed effects, as well as their implications for hardness assurance are discussed.