Symbolic function extraction and fault modelling of MOS circuits

This paper presents a new method for fault modelling of CMOS combinational circuits at the transistor level. Every transistor is replaced with a conductance controlled by the gate logic state. The specific advantage of the method is use of a symbolic simulator for circuit function extraction. This function is referred as the Transistor Logic Conductance Function (TLCF). Starting from a known TLCF a simple set of rules is used for output state determination. The method is suitable for multiple fault model generation thanks to the fact that only one symbolic analysis of a circuit is sufficient for modelling different stuck-open, stuck-short and stuck-at faults of a logic gate.