Design of three-state logic for CMOS VLSI digital systems

Problems and possibilities of three-state logic design for CMOS VLSI digital systems are considered in the paper. The algorithm for automatized design and optimization of CMOS three-state logic cells is proposed and described. It takes into account the most important aspects of cell design: scheme realization and cell optimization. The procedure for cell design depending on the concrete cell operation conditions inside the VLSI circuit is proposed. The conventional CMOS three-state circuits, and the CMOS three-state circuits with input hysteresis are considered. Original schemes of circuits with input hysteresis are also proposed.