Branch mechanisms in deep pipelines: reevaluating the existing solutions and proposing a new guideline

In this study we have shown that the ranking of the branch mechanisms changes when the underlined technology changes from the advanced CMOS, used for the state-of-the-art commercial microprocessors, to the more advanced technologies, that will probably be used in future microprocessors. New technologies as such GaAs or GaInAs imply deepening of the instruction pipeline. Hence, the problem studied here is important because branch instruction execution is one of the most serious causes of the performance degradation of deep pipeline processors. Software methods (Gross-Hennessy and Ignore), exhibiting an advantage compared to the elementary hardware schemes (Assume Branch Not Taken and Branch Target Buffer) in short pipelines, become inferior in deep pipelines.