Design and FPGA implementation of radix-10 algorithm for division with limited precision primitives

We present a radix-10 digit-recurrence algorithm for division using limited-precision multipliers, adders, and table-lookups. We describe the algorithm, a design, and its FPGA implementation. The proposed scheme is implemented on the Xilinx Virtex-5 FPGA device and we obtained the following characteristics: for n = 7, delay is ≈ 105ns and the cost is 782 LUTs. For n = 14, the implementation has a delay of ≈ 197ns and the cost of 1263 LUTs. The proposed scheme uses short operators which may have an advantage at the layout level and in power optimization.