New approaches for the reconfiguration of two-dimensional VLSI arrays using time-redundancy

Two novel approaches are presented in which no spare cells are used. They are based on the full processing utilization of fault-free cells by exploiting the single-product-step of a systolic array. This results in a reconfigured array with no degradation of computational speed. The basic principles of the time-redundancy technique are discussed, with particular emphasis on the selection and allocation processes for finding the reconfiguration-solution in real-time. The first approach is based on a distributed execution of the reconfiguration process. The immediate advantages of this approach are its simplicity of implementation and the fast execution time. The second approach is based on a more complex reconfiguration procedure that accounts for an iterative execution of the first approach. Appropriate conditions for its correct execution are presented.