Towards universal and voltage-scalable high gate- and drain-voltage MOSFETs in CMOS

This paper introduces a concept of lateral gates located on top of STI regions enabling layout-defined high gate voltages. Through the lateral fringing capacitance, conduction channels are opened also along the sidewalls of the STI regions leading to current flow along these sidewalls. The spacing between poly-Si and STI edge (= layout) determines gate dielectric thickness. Such novel Hybrid MOSFETs with both a high gate voltage and a high drain voltage capability are demonstrated experimentally in foundry baseline 65nm CMOS technology. Gate voltages up to 50V are measured including gate oxide integrity lifetime exceeding 10 years. The manufactured devices deliver current per micron on par with that of an ideal planar MOSFET with an equivalent gate-oxide thickness, but without a need for dedicated manufacturing steps.