PLL phase-noise modeling by PC

The linear model of phase locked loop which is proper for investigating of phase noise properties in the frequency domain is presented in this contribution. For simulation on PC analog-digital circuit analysis program Micro-Cap is used. Verification of the MC numerical simulations was done by MATLAB and measurements on the prototype were carried out. Based on numerical simulations results it is possible to verify basic theoretical relations and make a good PLL design. Using the mathematical analysis software MATLAB, along with the previous example, it will be possible to show how the various noise sources in a PLL can be modeled. A PSPICE noise macro models using the polynomial model of noise sources were tested successfully.