Combining internal scan chains and boundary scan register: A case study

The paper presents a Design-For-Testability (DFT) approach for System-on-Chips (SOC) that combines internal scan chains and boundary scan register (BSR) into a single scan register known as Scan-Through-TAP (STT) methodology. We are using the IEEE Standard 1149.1 Instruction as a user defined instruction (UDI) to control the internal scan chains operation via TDI and TDO saving the scan pins, and allowing accessibility of the internal scan chains at the board level through the TAP controller.