Optimum resolution-per-stage in high-speed pipelined A/D converters using self-calibration

The optimization of high-speed pipelined ADCs employing self-calibration techniques to achieve high-resolution is discussed. Different assignments of resolution-per-stage are explored taking into account such physical limitations as thermal noise and matching accuracy in the capacitor arrays. The impact of the selected pipeline configuration in the self-calibration requirements as well as in the feasibility of the active components is analyzed. A design example is presented to demonstrate the relevant conclusions.