Logic synthesis strategy for FPGAs with embedded memory blocks

With the evolution of programmable structures, that become more heterogeneous, the process of mapping a design into these structures becomes more and more complex. Modern FPGA chips are equipped with embedded memory blocks that can be used to increase the implementation quality of the design. The paper presents a logic synthesis method based on balanced decomposition that uses the concept of r-admissibility to efficiently utilize possibilities provided by memory blocks embedded in modern FPGA architectures. Results presented in this paper prove the effectiveness of proposed approach.