Design flow for CMOS based Class-E and Class-F power amplifiers

This paper presents the design flow for an integrated power amplifier. The flow is presented as a software routine. For a given set of amplifier specifications and CMOS process parameters, the routine computes the passive component values for a Class-E or Class-F based power amplifier. The routine includes the matching network for standard impedance loads. The routine also provides its user with a spiral inductor search algorithm, which can be used to generate layouts of inductors with Q-factors optimised at a desired frequency. For a typical power amplifier design case where several amplifiers are designed for application over different channels, the routine presented in this paper contributes by streamlining the design flow. The operation of the software routine was demonstrated by simulations in Austriamicrosystems 0.35 µm single-supply process for a 14 dBm, 2.4 GHz power amplifier design.