DocumentCode
3634366
Title
A 1.6 GB/s data-transfer-rate 8 Mb embedded DRAM
Author
S. Miyano;K. Numata;K. Sato;T. Yabe;M. Wada;R. Haga;M. Enkaku;M. Shiochi;Y. Kawashima;M. Iwase;M. Ohgata;J. Kumagai;T. Yoshida;M. Sakurai;S. Kaki;N. Yanagiya;H. Shinya;T. Furuyama;P. Hansen;M. Hannah;M. Nagy; Anan Nagarajan;M. Rungsea
Author_Institution
Toshiba Corp., Kawasaki, Japan
fYear
1995
Firstpage
300
Lastpage
301
Abstract
To realize high data-transfer rate in random access, several kinds of DRAMs with on-chip cache memory have been proposed. These DRAMs rely on locality of access to achieve the highest speed. However, in some graphic applications where sufficient locality of access is not expected, such DRAMs will not greatly accelerate system performance. Embedded memories have benefits for such applications due to their wide data bus and band width. The 8 Mb embedded DRAM presented in this paper provides 1.6 GB/s data transfer rate and realizes 10 ns cycle random access without page fault delay.
Keywords
"Random access memory","Flip-flops","Fault tolerance","Application specific integrated circuits","Power supplies","Delay","Timing","Joining processes","Circuit faults","CMOS process"
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
ISSN
0193-6530
Print_ISBN
0-7803-2495-1
Type
conf
DOI
10.1109/ISSCC.1995.535564
Filename
535564
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