Design and performance of the ABCN-25 readout chip for ATLAS Inner Detector Upgrade

We present the design and performance of the ABCN-25 readout chip implemented in 0.25 μm CMOS technology. The front-end design has been optimized for the short, 2.5 cm, silicon strips foreseen in the upgrade of the ATLAS Inner Detector. The core of the readout architecture includes binary front-end, two levels of data buffering, data compression and data serializing circuitry, and is similar to the architecture of the ABCD3T chip used in the present ATLAS SCT detector. In order to ensure required radiation hardness the hardening by layout technique has been used and SEU detection and correction circuitry have been added. The design includes on-chip power management circuitry comprising two types of shunt regulators and a serial regulator. This circuitry makes the ABCN-25 chip compatible with recent developments in the area of power distribution systems for the inner trackers in the SuperLHC environment and in particular with serial powering of the detector modules. The chip has been fabricated in 0.25 μm CMOS technology and full functionality has been obtained. The critical design aspects and performance of the analog and digital circuits will be presented and discussed.