Testability improvement in high-level synthesis through reconvergence reduction

Justification of multiple circuit lines in automatic test pattern generation (ATPG) is exponential in complexity in the presence of reconvergent fanout. Reconvergent fanout consequently is a chief source of increased complexity in the ATPG process. Reconvergence also degrades the pseudo-random test by producing correlation between inputs of the same combinational logic block. Consideration of reconvergence during synthesis can result in its elimination at minimal area or performance cost. The high regularity of DSP architectures facilitates reconvergence reduction, when, it is addressed during synthesis. We present a design-for-testability approach to remove reconvergence during high-level synthesis. We have developed a method for estimating the degree of reconvergence, based on an estimate of the existence of paths between each pair of hardware units. We have designed and implemented scheduling and binding algorithms which use the proposed reconvergence estimate to consistently direct synthesis to RTL datapaths with reduced reconvergent fanout. The experimental results shown demonstrate the effectiveness of the proposed methodology.