Selective Epitaxial Bipolar Technology for 25 to 40 Gb/s ICs

A silicon bipolar technology, which uses Selective Epitaxial Growth (SEG) for the active base and collector regions is described. Key features of the SEG transistor configuration are a quasi self-aligned base/collector structure and an epitaxial base process, which has been integrated into a self-aligned double-poly emitter/base configuration. The high speed capability of the SEG transistor concept has been proven by CML gate delay times of 18 ps. In addition several ICs (2:1 static frequency divider, time division multiplexer, demultiplexer) suited for optical-fibre links and measurement equipment have been fabricated.