A Compact Parallel (31,5)-Counter Circuit Based on Capacitive Threshold-Logic Gates

A novel high-speed circuit implementation of the (31,5)-counter (i.e., the 31-bit data compressor) based on capacitive threshold logic (CTL) is presented. The circuit consists of 20 threshold logic gates arranged in two stages. The charge-based CTL gates are essentially dynamic circuits which require a periodic refresh or precharge cycle, but unlike conventional dynamic CMOS gates, the circuit can be operated in synchronous as well as in asynchronous mode. The compressor circuit is implemented using conventional 1.2 ?m double-poly CMOS technology, and it occupies a silicon area of (583 ? 297) ?m². Experimental results indicate that the test circuit has a maximum input-to-output propagation delay of 40 ns, and it is shown to operate reliably when consecutive 31-bit input vectors are applied at a rate of up to 16 Mvectors/s, which corresponds to a data processing capability of about 500 Mbits/s.