A novel device — Floating gate transistor for storing weight of neural networks

This paper deals with operation of a floating gate transistor as a memory element. The aim was to simulate and analyze operation and properties of the memory transistor with a so-called pseudo-gate depending upon changes of various parameters and to optimize this structure for AMS CMOS 0.35 μm technology. Tunneled charge carriers in floating gate are trapped in here and this affects the behavior of this structure. We examined the memory behavior based on erasing, writing and transfer characteristics in dependence on the amount of trapped charge. On the basis of our analysis we recommended the structure of memory element as a base for implementation in a neural network.