Versatile sub-bandgap reference IP core

A step-by-step design procedure of sub-bandgap voltage reference (BGR) is proposed. The procedure shows on example structure main design steps of crucial parameters verified later by a simulation. The block is meant to be fabricated in 0.35 μm CMOS process with analog options. The main features of the concept are the sub-bandgap output voltage of 0.7 V, low supply voltage from 1.3 V, low power consumption under 10 μA, versatility, high working temperature range from -50 to 95°C. The versatility of the block is supported by a temperature slope trimming, extended start-up and self testing. The IP block is compact, ready to adjust, layout and integrate. The features of the design also allow the in circuit tuning. This example circuit shows the use of the design algorithm including the optimization suggestions which lead to a complex design.