DocumentCode :
3636907
Title :
Effect of parasitic RLC parameters in bias networks on ECL delay time
Author :
E. Mavrek;I. Lončarić;I. Poljak;M. Koričić;T. Suligoj
Author_Institution :
Department of Electronics, Microelectronics, Computing and Intelligent Systems, Faculty of Electrical Engineering and Computing, University of Zagreb, Unska 3, HR- 10 000, Croatia
fYear :
2010
Firstpage :
73
Lastpage :
77
Abstract :
Emitter coupled logic (ECL) ring oscillator with typical integrated bipolar transistor is examined. Waveform stability and propagation delay time are studied with respect to the parasitic RLC components in bias voltage resistance and the limited dimensions of circuit metallization. It is shown that the parasitic components in reference and current-source network of ECL inverter, for differential pair current (IC) of 300 µA, don´t have a significant effect. Results indicate that propagation delay time and waveform stability mostly depend on parasitic components in the supply network. Moreover, propagation delay time depends on parasitic resistances and the stability depends on parasitic inductances.
Keywords :
"Delay effects","Propagation delay","Circuit stability","Coupling circuits","Logic","Ring oscillators","Bipolar transistors","Voltage","RLC circuits","Metallization"
Publisher :
ieee
Conference_Titel :
MIPRO, 2010 Proceedings of the 33rd International Convention
Print_ISBN :
978-1-4244-7763-0
Type :
conf
Filename :
5533395
Link To Document :
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