Evaluation of embedded processor based BDD implementation

Different strategies for implementation of computationally intensive applications in hardware are available today. The spectrum of implementations ranges from usage of standardized microprocessors to specially tailored hardware solutions. Available processor architectures range from general purpose type through processors with instruction set extensions to application-specific processors. On the other side, recent advances in design automation resulted in development of C-to-hardware compilers as a new strategy for application implementation in hardware. In this paper, we present and elaborate characteristics of hardware implementations of Binary Decision Diagrams (BDDs) application, used in many research and development areas, and especially in formal verification and Computer-Aided Design (CAD) tools. For this application, processor architecture using C-to-hardware NISC toolset is manually tailored and compared with implementation approaches based on standard soft and hard processors. All these approaches are implemented and verified using FPGA Virtex-5 development board. Our results show that, besides code and compiler side optimizations, more significant improvements in total execution cycles count can be achieved when processor architecture side optimizations are included.