Parallel sparse matrix solver for direct circuit simulations on FPGAs

As part of our effort to parallelise SPICE simulations over multiple FPGAs, we present a parallel FPGA implementation for a sparse matrix solver optimised for execution on a single FPGA node. Our approach combines static pivoting with symbolic analysis to compute an accurate task flow-graph which efficiently exploits parallelism at multiple granularities and sustains high floating-point data rates. The sparse matrix solver is tested with circuit simulation matrices from the University of Florida matrix collection. We report a 10–30X speedup compared to a 2.4 GHz Intel Core Duo processor running UMFPACK, a state-of-the-art sparse matrix solver.