• DocumentCode
    3637542
  • Title

    A 5.8mW 3GPP-LTE compliant 8×8 MIMO sphere decoder chip with soft-outputs

  • Author

    Chia-Hsiang Yang;Tsung-Han Yu;Dejan Marković

  • Author_Institution
    Electrical Engineering Department, University of California, Los Angeles, USA
  • fYear
    2010
  • Firstpage
    209
  • Lastpage
    210
  • Abstract
    A MIMO chip for 3GPP-LTE standard and beyond is described. The chip implements sphere decoding algorithm with 16-core architecture. The chip is flexible to support multiple configurations: antenna arrays from 2×2 to 8×8, modulations from BPSK to 64QAM, FFT sizes from 128 to 2048 and hard/soft outputs. The chip dissipates 5.8mW for the 3GPP-LTE standard in 3.35mm2 area in 65nm CMOS.
  • Keywords
    "MIMO","Decoding","Registers","Computer architecture","Kernel","Antenna arrays"
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2010 IEEE Symposium on
  • Print_ISBN
    978-1-4244-5454-9
  • Type

    conf

  • DOI
    10.1109/VLSIC.2010.5560294
  • Filename
    5560294
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3637542