Sparse Matrix-Vector Multiplication Based on Network-on-Chip in FPGA

A new method for performing Sparse Matrix–Vector Multiplication (SMVM) by using Network–on–Chip (NoC) architecture is described. In traditional IC design on-chip communications have been designed with dedicated point–to–point interconnections or shared–buses. Therefore, regular local data transfer is the major concern of many parallel implementations. However, when dealing with the parallel implementation of SMVM, which is the main step of all iterative algorithms for solving system of linear equations, the required data transfers depend on the sparsity structure of the matrix and can be extremely irregular. Using a NoC architecture makes it possible to deal with arbitrary structure of the data transfers; i.e. with the irregular structure of the sparse matrices. So far, we have implemented the proposed SMVM calculator based on NoC architecture with the size of 4×4 and 5×5 in IEEE 754 single float point precision using FPGA.