Optimization of multiplexer trees using modified truth table

The paper presents a novel method of multiplexer tree design. An n-to-1 multiplexer is generally implemented by decomposition into smaller multiplexers (2-to-1 usually but 16-to-1 at max). We proposed efficient method for elimination multiplexers or group of multiplexers from a circuit according to our several rules. The final circuit can be made of multiplexers and also basic logic gates such as AND, NAND, OR, NOR, etc. An illustrated example and experiments are presented in the paper. The experimental results shows that our proposed method can decrease number of used gates up to 32,23 % compared to original circuit.