Embedded systems with increased reliability using the multiple watchdog timers approach

The safety of the real-time processes in embedded systems is nowadays commonly ensured by the watchdog timer mechanism. Although this method is generally considered as reliable, there exists a certain risk that the hardware watchdog timer that is standardly shared by many processes, would become unusable because of incorrect handling by a broken process. This paper deals with the architecture providing multiple hardware watchdog timers to the system. It describes in detail the basic concept of the system, its architecture and the prototype implementation.