An implementation of BCH codes in a FPGA

Our paper presents the prototyping of a BCH (Bose, Chaudhuri, and Hocquenghem) encoder and decoder using a Field Programmable Gate Array (FPGA) reconfigurable chip. These types of codes are used in communications networks to detect and correct errors. Typically, the algorithms that implement these codes are sequentially type. Our solution is a combination of a parallel and a sequential implementation. We implemented the BCH code in a 3s400FG456 FPGA. In this implementation we used 15 bits-size word code and the results show that the circuits work quite well.