• DocumentCode
    3638456
  • Title

    Reconfigurable Fault-Tolerant System Sychronization

  • Author

    Jan Balach;Ondrej Novak

  • Author_Institution
    Dept. of Digital Design, Czech Tech. Univ. in Prague, Prague, Czech Republic
  • fYear
    2010
  • Firstpage
    817
  • Lastpage
    820
  • Abstract
    A method and architecture for synchronization of Fault-Tolerant system implemented in FPGAs is proposed. It is based on repairing faulty units and transferring of the fault-free state of the system to the unit under repair. Its architecture is based on the previously designed model which is extended for usage in more complex systems. The proposed method was implemented on an FPGA and the experimental architecture with an analysis of the results is given.
  • Keywords
    "Field programmable gate arrays","Computer architecture","Integrated circuit modeling","Data models","Protocols","Fault tolerance","Fault tolerant systems"
  • Publisher
    ieee
  • Conference_Titel
    Digital System Design: Architectures, Methods and Tools (DSD), 2010 13th Euromicro Conference on
  • Print_ISBN
    978-1-4244-7839-2
  • Type

    conf

  • DOI
    10.1109/DSD.2010.103
  • Filename
    5615463
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3638456