Title :
Tri-gate bulk CMOS technology for improved SRAM scalability
Author :
Changhwan Shin;Borivoje Nikolic;Tsu-Jae King Liu;Chen Hua Tsai;Mei Hsuan Wu;Chung Fu Chang;You Ren Liu;Chih Yang Kao;Guan Shyan Lin;Kai Ling Chiu;Chuan-Shian Fu;Cheng-tzung Tsai;Chia Wen Liang
Author_Institution :
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, 94720-1770 USA
Abstract :
A simple approach for manufacturing quasi-planar tri-gate bulk MOSFET structures is demonstrated and shown to be effective for reducing variation in 6T-SRAM read and write margins, in an early 28nm CMOS technology. With optimization of the pocket implant doses, quasi-planar bulk CMOS technology can facilitate voltage scaling. It also provides a means to achieve high yield with a notch-less 6T-SRAM cell layout, to facilitate area scaling.
Keywords :
"Random access memory","Logic gates","MOS devices","CMOS integrated circuits","CMOS technology","MOSFET circuits","Performance evaluation"
Conference_Titel :
Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European
Print_ISBN :
978-1-4244-6658-0
DOI :
10.1109/ESSDERC.2010.5618437
