• DocumentCode
    3638657
  • Title

    BiCMOS gate array circuits

  • Author

    Xuhong Hu; Meiyuan Wang; Min Zhang

  • Author_Institution
    Inst. of Metall., Acad. Sinica, Shanghai, China
  • fYear
    1996
  • Firstpage
    333
  • Lastpage
    335
  • Abstract
    BiCMOS gate array circuits and macrocell libraries are designed and fabricated through 2.0 /spl mu/m BiCMOS standard processes. The average gate delay time is as follows: BiCMOS 21 stage inverter, 1.1 ns; BiCMOS 21 stage oscillator, 1.1 ns; BiCMOS 21 stage NAND, 1.3 ns; BiCMOS 21 stage NOR, 1.4 ns. BiCMOS 500 gate array circuits are optimized and 2000 gate array circuits are designed. The delay time of BiCMOS is less than CMOS with large load capacitance.
  • Keywords
    "BiCMOS integrated circuits","Delay effects","Inverters","MOSFETs","Bipolar transistors","Parasitic capacitance","Macrocell networks","Propagation delay","Microelectronics","Libraries"
  • Publisher
    ieee
  • Conference_Titel
    ASIC, 1996., 2nd International Conference on
  • Print_ISBN
    7-5439-0940-5
  • Type

    conf

  • DOI
    10.1109/ICASIC.1996.562821
  • Filename
    562821
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3638657