Exploitation of scattered context grammars to model VLIW instruction constraints

More and more nowadays data processing System-on-Chip (SoC) devices exploit the very long instruction word (VLIW) technology. The high performance of VLIW processors is achieved by a high instruction level parallelism. Program execution is scheduled statically at compilation time. Therefore, there is no need for run-time control mechanisms and hardware can be relatively simple. On the other hand, all constraints checks must be done by the compiler. This paper describes formal method for modeling instruction level limitations of these processors. This method is based on scattered context grammars that generate proper assembler code. This concept has two advantages - formal description of the dependency checking process and high reduction of description complexity over other methods.