Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs

In this paper, we propose a novel fault-tolerance scheme, band reconfiguration, to handle multiple permanent faults in functional units of general ASIC designs. An associated high-level synthesis procedure that automatically generates such fault-tolerant systems is also presented. The proposed scheme permits multiple levels of graceful degradation. During each reconfiguration the system instantly reconfigures itself through operation rescheduling and hardware rebinding. The design objectives are optimization of resource utilization rate under each configuration, and reduction of hardware and performance overheads. The proposed high-level synthesis approach enables fast and area-effective implementations of gracefully degradable ASICs.