Reconfigurable Cache Implemented on an FPGA

Cache memory is a common structure in computer system and has an important role in microprocessor performance. A relationship between the performance of particular algorithm and main cache parameters such as associativity, number of words per block and cache size has been demonstrated. In this paper, we propose a reconfigurable cache with several working modes. The cache was physically implemented on an FPGA, connected to an embedded processor and tested for different algorithms, profiting the configuration facilities of these devices. A test platform was also developed. We report some performance parameters of interest.