Hierarchical partitioning

Partitioning of digital circuits has become a key problem area during the last five years. Benefits from new technologies like Multi-Chip-Modules or logic emulation strongly depend on partitioning results. Most published approaches are based on abstract graph models constructed from flat netlists, which consider only connectivity information. The approach presented in this paper uses information on design hierarchy in order to improve partitioning results and reduce problem complexity. Designs up to 150 k gates have been successfully partitioned by descending and ascending the hierarchy. Compared to. Standard k-way iterative improvement partitioning approach results are improved by up to 65% and runtimes are decreased by up to 99%.