• DocumentCode
    3640334
  • Title

    Low power sensor node processor architecture

  • Author

    Goran Panic;Thomas Basmer;Klaus Tittelbach-Helmrich;Lukasz Lopacinski

  • Author_Institution
    IHP, Frankfurt Oder, Germany
  • fYear
    2010
  • Firstpage
    914
  • Lastpage
    917
  • Abstract
    This paper presents a low power solution for sensor node processor architecture, where an asynchronous processor has been integrated with a number of peripherals in a quite unique fashion. The paper describes the most important architectural and design issues and presents the implementation results.
  • Keywords
    "Variable speed drives","Latches","Anodes","Baseband","Layout"
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on
  • Print_ISBN
    978-1-4244-8155-2
  • Type

    conf

  • DOI
    10.1109/ICECS.2010.5724661
  • Filename
    5724661
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3640334