Title :
Low power sensor node processor architecture
Author :
Goran Panic;Thomas Basmer;Klaus Tittelbach-Helmrich;Lukasz Lopacinski
Author_Institution :
IHP, Frankfurt Oder, Germany
Abstract :
This paper presents a low power solution for sensor node processor architecture, where an asynchronous processor has been integrated with a number of peripherals in a quite unique fashion. The paper describes the most important architectural and design issues and presents the implementation results.
Keywords :
"Variable speed drives","Latches","Anodes","Baseband","Layout"
Conference_Titel :
Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on
Print_ISBN :
978-1-4244-8155-2
DOI :
10.1109/ICECS.2010.5724661
