DocumentCode

3640621

Title

High-speed Clock Distribution Architecture Employing PLL For O.6/spl mu/m CMOS SOG

fYear

1992

fDate

6/14/1905 12:00:00 AM

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1992., Proceedings of the IEEE 1992

Print_ISBN

0-7803-0246-X

Type

conf

DOI

10.1109/CICC.1992.591859

Filename

5727418