• DocumentCode
    3641923
  • Title

    Scalability and design-space analysis of a 1T-1MTJ memory cell

  • Author

    Richard Dorrance;Fengbo Ren;Yuta Toriyama;Amr Amin;C.-K. Ken Yang;Dejan Marković

  • Author_Institution
    Department of Electrical Engineering, University of California, Los Angeles, USA
  • fYear
    2011
  • fDate
    6/1/2011 12:00:00 AM
  • Firstpage
    32
  • Lastpage
    36
  • Abstract
    This paper introduces a design-space feasibility region as a function of MTJ characteristics and memory target specifications. The sensitivity of the design space is analyzed for scaling of both MTJ and underlying transistor technology. Design points for improved yield, density, and memory performance can be extracted for 90nm down to 32nm processes based on measured MTJ devices. To achieve flash-like densities in upcoming 22nm and 16nm technology nodes, scaling of the critical switching current density is required.
  • Keywords
    "Magnetic tunneling","Computer architecture","Microprocessors","Switches","Random access memory","Decision support systems","Tunneling magnetoresistance"
  • Publisher
    ieee
  • Conference_Titel
    Nanoscale Architectures (NANOARCH), 2011 IEEE/ACM International Symposium on
  • Print_ISBN
    978-1-4577-0993-7
  • Type

    conf

  • DOI
    10.1109/NANOARCH.2011.5941480
  • Filename
    5941480
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3641923