Radiation hardening by design: A novel gate level approach

Soft errors induced by radiation, causing malfunctions in electronic systems and circuits, have become one of the most challenging issues that impact the reliability of the modern processors even in sea-level applications. In this paper we present two novel radiation-hardening techniques at Gate-level. We present a Single-Event-Upset (SEU) tolerant Flip-Flop design with 38% less power overhead and 25% less area overhead at 65nm technology comparing to the conventional Triple Modular Redundancy (TMR) for Flip-Flop design. We also present an SEU-tolerant Clock-Gating scheme with less than 50% area-power overheads and no performance penalty comparing to the conventional TMR for clock-gating. Our simulations show that the proposed schemes can recover from SEU errors in 99% of the cases.