• DocumentCode
    3643119
  • Title

    A 75µW, 16-channel neural spike-sorting processor with unsupervised clustering

  • Author

    Vaibhav Karkare;Sarah Gibson;Chia-Hsiang Yang;Henry Chen;Dejan Marković

  • Author_Institution
    Electrical Engineering Department, University of California, Los Angeles, USA
  • fYear
    2011
  • fDate
    6/1/2011 12:00:00 AM
  • Firstpage
    252
  • Lastpage
    253
  • Abstract
    We describe a neural spike-sorting processor that provides unsupervised clustering simultaneously for 16 channels. The use of a two-stage clustering algorithm, noise-tolerant distance metric, and selectively clocked high-VT register arrays makes online clustering feasible for implementation. The spike-sorting processor has a power consumption of 75μW at 270mV and an area of 2.45mm2 in a 65nm CMOS.
  • Keywords
    "Clustering algorithms","Sorting","Clocks","Transient analysis","Registers","Accuracy","Memory management"
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2011 Symposium on
  • ISSN
    2158-5601
  • Print_ISBN
    978-1-61284-175-5
  • Electronic_ISBN
    2158-5636
  • Type

    conf

  • Filename
    5986133
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3643119