Managing variability for ultimate energy efficiency

Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate the choice of technology, architecture, and implementation techniques that trade off performance for power savings. Energy-efficient design is often achieved for designs that are sensitive to technology and design parameters. On the other hand, increased variability in semiconductor process technology and devices requires added margins in the design to guarantee the desired yield. Sources of variability in scaled technologies are reviewed, along with models and methods for their capture in design. Variability is characterized with respect to the distribution of its components, its spatial and temporal characteristics and its impact on specific circuit topologies. Methods of desensitizing the digital logic and SRAM to variability at low supply voltages are demonstrated.