Implementation of a 64-bit hybrid SR-ARQ algorithm on FPGA

Forward error correction (FEC) and automatic request (ARQ) are common techniques used to treat transmission errors when data are transmitted over noisy channels. In practical applications where feedback is possible, ARQ technique are often more preferable than FEC schemes because error detection requires much simpler decoding equipment and achieves a higher reliability than does error correction. When the channel is very noisy, the system throughput is smaller for ARQ techniques than FEC schemes because retransmission will be requested too frequently. Hybrid Selective Repeat automatic request schemes (H SR-ARQ), which combine the concepts of FEC and ARQ can provide a high system throughput and maintain high system reliability for communications over quite noisy channel. To increase the speed of communication, we implement an H SR-ARQ hardware system. We choose Field Programmable Gate Array (FPGA) circuit for hardware implementation because it is flexible, easy to program and low cost and obtain good performances in communication.