Efficiency improvement of power amplifiers without degraded linearity using a new topology and control method

This paper presents a medium-power amplifier designed in class AB at 2.4 GHz with two transistors of the same type in parallel. Keeping the drain bias of the transistors constant, it is demonstrated that by careful selection of the transistor and dynamically tuning the gate bias of the individual devices and output matching of the whole amplifier according to input drive level, an increase of about 40% in PAE is achieved at 7 dB back-off from the P1dB of the class AB amplifier employing a fixed bias and matching network and giving the same maximum output power. On the other hand, at higher drive levels while maintaining the PAE nearly constant (the same situation that is experienced in Doherty techniques), a maximum improvement of 7 dB can be observed at 1 dB compression point.